TAS5715
www.ti.com
SLOS645 –AUGUST 2010
SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
fSCLKIN
tsu1
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
Setup time, LRCLK to SCLK rising edge
Hold time, LRCLK from SCLK rising edge
Setup time, SDIN to SCLK rising edge
Hold time, SDIN from SCLK rising edge
LRCLK frequency
CL = 30 pF
1.024
10
3.072
MHz
ns
th1
10
ns
tsu2
10
ns
th2
10
ns
8
48
50%
50%
48
60%
60%
kHz
SCLK duty cycle
40%
40%
LRCLK duty cycle
SCLK
edges
SCLK rising edges between LRCLK rising edges
32
64
t(edge)
tr/tf
SCLK
period
LRCLK clock edge with respect to the falling edge of SCLK
Rise/fall time for SCLK/LRCLK
–1/4
1/4
8
ns
tr
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 2. Slave Mode Serial Data Interface Timing
Copyright © 2010, Texas Instruments Incorporated
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