TAS5705
www.ti.com ...................................................................................................................................................................................................... SLOS549–JUNE 2008
CLOCK CONTROL REGISTER (0x00)
In the manual mode, the clock control register provides a way for the system microprocessor to update the data
and clock rates based on the sample rate and associated clock frequencies. In the autodetect mode, the clocks
are automatically determined by the TAS5705. In this case, the clock control register contains the autodetected
FS and MCLK status as automatically detected (D7–D2). Bits D7–D5 select the sample rate. Bits D4–D2 select
the MCLK frequency. Bit D0 is used in manual mode only. In this mode, when the clocks are updated a 1 must
be written to D0 to inform the DAP that the written clocks are valid.
Table 8. Clock Control Register (0x00)
D7
0
0
0
0
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
D6
0
0
1
1
0
0
1
1
–
–
–
–
–
–
–
–
–
–
–
D5
0
1
0
1
0
1
0
1
–
–
–
–
–
–
–
–
–
–
–
D4
–
–
–
–
–
–
–
–
0
0
0
0
1
1
1
–
–
–
D3
–
–
–
–
–
–
–
–
0
0
1
1
0
0
1
–
–
–
D2
–
–
–
–
–
–
–
–
0
1
0
1
0
1
X
–
–
–
D1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
–
–
D0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
1
FUNCTION
fS = 32-kHz sample rate
fS = 38-kHz sample rate
fS = 44.1-kHz sample rate
fS = 48-kHz sample rate
fS = 88.2-kHz sample rate
fS = 96-kHz sample rate
(1)
fS = 176.4-kHz sample rate
fS = 192-kHz sample rate
(2)
MCLK frequency = 64 × fS
MCLK frequency = 128 × fS
MCLK frequency = 192 × fS
(3)
(1)
MCLK frequency = 256 × fS
MCLK frequency = 384 × fS
(4)
MCLK frequency = 512 × fS
Reserved
(1)
Bit clock (SCLK) frequency = 64 × fS or 32 × fS (selected in register 0x04)
(5)
Bit clock (SCLK) frequency = 48 × fS
(1)
Clock not valid (in manual mode only)
Clock valid (in manual mode only)
(1) Default values are in bold.
(2) Rate not available for 32-, 44.1-, and 48-kHz data rates
(3) Rate not available for 32-kHz data rate
(4) Rate not available for 176.4-kHz and 192-kHz data rates
(5) Rate only available for 192-fS and 384-fS MCLK frequencies
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 9. General Status Register (0x01)
D7
0
D6
–
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
(1)
Default
Identification code
–
0
1
0
0
0
0
1
(1) Default values are in bold.
Copyright © 2008, Texas Instruments Incorporated
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