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SLOS563 – MARCH 2008
ELECTRICAL CHARACTERISTICS
DC Characteristics, T
A
= 25°C, PVCC_X, AVCC = 18 V, DVDD = AVDD = 3.3 V, R
L
= 8
Ω
(unless otherwise noted)
PARAMETER
V
OH
V
OL
| VOS |
V
BYPASS
High-level output voltage
Low-level output voltage
Class-D output offset voltage
PVCC/8 reference for analog section
LRCLK, SCLK, SDINx, MCLK,
GAIN_x
VREG_EN, FORMATx,
CONFIG_x
BKND_ERR, RESET, PDN,
MUTE
RESET, PDN, MUTE, GAIN_x,
BKND_ERR
I
IH
High-level input current
VREG_EN, FORMAT_x,
CONFIGx, LRCLK, SCLK,
SDINx, MCLK
RESET, PDN, MUTE, LRCLK,
SCLK, SDINx, MCLK, GAIN_x
No load
V
I
= 0 V, DVDD = 3.6 V
2.2
3.3-V TTL and 5-V tolerant
3.3-V TTL and 5-V tolerant
(1)
(1)
TEST CONDITIONS
I
OH
= –4 mA
I
OL
= 4 mA
MIN
2.4
TYP MAX
0.5
±26
2.26
2.3
±2
UNIT
V
V
mV
V
I
IL
Low-level input current
µA
V
I
= 0 V, DVDD = 3.6 V
V
I
= 3.6 V, DVDD = 3.6 V
V
I
= 3.6 V, DVDD = 3.6 V
V
I
= 5.5 V, DVDD = 3.6 V
Normal mode
65
8
23
14
33
58
58
60
240
V
CC
= 18 V , I
O
= 500 mA,
T
J
= 25°C
C
(BYPASS)
= 1
µF,
Time required for the
BYPASS pin to reach its
final value
240
480
500
30
500
30
850
ms
ms
mΩ
±50
±2
±50
±50
80
16
33
57
176
176
mA
µA
µA
dB
mA
µA
I
DD
Digital supply current
Supply voltage (DVDD, AVDD)
Power down
(PDNZ = LOW)
Reset (RESET = LOW)
No load
No load
No load
PVCC = 17.5 V to 18.5 V
I
CC
I
CC(RESET)
I
CC(PDNZ)
PSRR
R
DS(on)
Quiescent supply current
Quiescent supply current in reset mode
Quiescent supply current in power down mode
DC power-supply rejection ratio
Drain-source on-state resistance, high-side
Low-side
Total
Turnon time (SE mode) (CONFIG_2 = 0)
Turnon time (BTL mode) (CONFIG_2 = 1)
Turnoff time (SE mode) (CONFIG_2 = 0)
(2)
Turnoff time (BTL mode) (CONFIG_2 = 0)
(2)
t
ON
t
OFF
(1)
(2)
5-V tolerant pins are PDN, RESET, MUTE, SCLK, LRCLK, MCLK, SDIN1, and SDIN2.
For
pop-free
power-off (PVDD = 0 V), it is recommended that PDN be cycled low for at least this period of time before PVDD drops
below 10 V and DVDD drops below 3 V.
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