SLOS563 – MARCH 2008
www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
BST_B
BST_C
BST_D
BYPASS
CONFIG_1
CONFIG_2
DVDD
DVSS
DVSSO
FORMAT0
FORMAT1
FORMAT2
GAIN_0
GAIN_1
LRCLK
MCLK
MUTE
NO.
61
53
55
56
34
33
15,
35
26
20
32
31
30
29
28
22
36
21
TYPE
(1)
5-V
TOLERANT
TERMINATION
(2)
DESCRIPTION
High-side bootstrap supply for half-bridge B
High-side bootstrap supply for half-bridge C
High-side bootstrap supply for half-bridge D
Nominally equal to V
CC
/8. Internal reference voltage for analog cells
P
P
P
O
P
P
P
P
P
DI
DI
DI
DI
DI
DI
DI
DI
5-V
5-V
5-V
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Input/output configuration.
Input/output configuration.
3.3-V digital power supply
Digital ground
Oscillator ground
Digital data format select.
Digital data format select.
Digital data format select.
LSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
MSB of gain select. GAIN_0 and GAIN_1 allow 4 possible gain
selections.
Input serial audio data left/right clock (sampling rate clock)
Master clock input. The input frequency of this clock can range from
4.9 MHz to 49.2 MHz.
Performs a soft mute of outputs, active-low. A logic low on this
terminal sets the outputs equal to 50% duty cycle. A logic high on this
terminal allows normal operation. The mute control provides a
noiseless volume ramp to silence. Releasing mute provides a
noiseless ramp to previous volume.
Oscillator trim resistor. Connect an 18.2-kΩ resistor to DVSSO.
Output, half-bridge A
Output, half-bridge B
Output, half-bridge C
Output, half-bridge D
OSC_RES
OUT_A
OUT_B
OUT_C
OUT_D
PDN
19
4, 5
1, 64
49,
50
45,
46
17
AO
O
O
O
O
DI
5-V
Pullup
Power down, active-low. PDN stops all clocks and outputs stop
switching. When PDN is released, the device powers up all logic,
starts all clocks, and performs a soft start that returns to the previous
configuration. Changes to CONFIG_x, FORMATx, and GAIN_x pins
are ignored on PDN cycling.
Power ground for half-bridge A
Power ground for half-bridge B
Power ground for half-bridge C
Power ground for half-bridge D
PLL negative loop filter terminal
PLL positive loop filter terminal
Power supply input for half-bridge output A
Power supply input for half-bridge output B
Power supply input for half-bridge output C
Power supply input for half-bridge output D
PGND_A
PGND_B
PGND_C
PGND_D
PLL_FLTM
PLL_FLTP
PVCC_A
PVCC_B
PVCC_C
PVCC_D
6, 7
2, 3
47,
48
43,
44
12
13
8, 9
62,
63
51,
52
41,
42
P
P
P
P
AO
AO
P
P
P
P
6
Product Folder Link(s):
Copyright © 2008, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
