Pin Assignments
47
73
BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
DUAL J-K FLIP-FLOPS WITH CLEAR
OUTPUTS
VCC
f
g
a
b
c
d
e
1J
1Q
1Q
GND
2K
2Q
2Q
16 15 14 13 12 11 10
9
14 13 12 11 10
9
8
f
g
a
b
c
d
e
Q
J
Q
Q
Q
J
CLR
CLR
BI/
B
C
LT RBO RBI
D
A
CK
CK
K
K
1
2
3
4
5
6
7
8
GND
1
2
3
1K
4
5
6
7
2J
B
C
LAMP RB
TEST OUT-
PUT
RB
D
A
IN-
1CK 1CLR
V
2CK 2CLR
CC
PUT
INPUTS
INPUTS
See page 258
See page 262
51
74
AND-OR-INVERT GATES
DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
`51, `S51 DUAL 2-WIDE 2-INPUT
positive logic:
Y = AB + CD
MAKE NO EXTERNAL CONNECTION
VCC 1B 1D
V
2CLR
2D
2CK
2PR
2Q
2Q
CC
1C
1Y
14 13 12 11 10
9
8
14 13 12 11 10
9
8
PR
D
CK
Q
Q
CLR
CLR
PR
Q
Q
CK
D
1
1CLR
2
1D
3
1CK
4
1PR
5
1Q
6
1Q
7
GND
1
2
3
4
5
6
7
1A
2A
2B
2C
2D
2Y
GND
See page 264
AND-OR-INVERT GATES
`LS51 2-WIDE 3-INPUT, 2-WIDE 2-INPUT
positive logic:
75
4-BIT BISTABLE LATCHES
1Y = (1A 1B 1C) + (1D 1E 1F)
2Y = (2A 2B) + (2C 2D)
ENABLE
1–2
1Q
2Q
2Q
GND
3Q
3Q
4Q
VCC
1C
1B
1F
1E
1D
1Y
16 15 14 13 12 11 10
9
14 13 12 11 10
9
8
Q
Q
D
G
D
G
Q
Q
Q
Q
D
G
D
G
Q
Q
1
1Q
2
1D
3
4
5
6
3D
7
4D
8
4Q
1
1Y
2
2A
3
2B
4
2C
5
2D
6
2Y
7
GND
2D ENABLE
V
CC
3–4
See page 260
See page 266
64
85
4-2-3-2 INPUT AND-OR INVERT GATES
positive logic:
4-BIT MAGNITUDE COMPARATORS
DATA INPUTS
A1
Y = ABCD + EF + GHI + JK
V
CC
A3
B2
A2
B1
A0
B0
V
D
C
B
K
J
Y
CC
16 15 14 13 12 11 10
9
14 13 12 11 10
9
8
A3
B3
B2
A2
A1
B1
A0
B0
A<B
IN
A=B
IN
A>B
IN
A>B
OUT
A=B
OUT
A<B
OUT
1
2
3
4
5
A>B
6
7
A<B
8
GND
1
A
2
E
3
F
4
G
5
H
6
I
7
GND
B3
A<B
A=B
A>B
A=B
DATA
INPUT
CASCADE INPUTS
OUTPUTS
See page 261
See page 267
165
TI [ TEXAS INSTRUMENTS ]
