2G74
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
Logic Diagram
7
PRE
1
C
CLK
C
C
5
Q
TG
C
C
C
C
2
6
D
TG
TG
TG
3
Q
C
C
C
CLR
FUNCTION TABLE
INPUTS
PRE CLR CLK
OUTPUTS
D
Q
Q
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
↑
↑
L
X
X
X
H
L
H
L
H
H
L
L
H
H
L
†
†
H
X
Q
Q
0
0
† This configuration is nonstable; that is, it does not persist
when PRE or CLR returns to its inactive (high) level.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
PARAMETER
MAX or MIN
UNIT
ICC
IOH
IOL
MAX
MAX
MAX
0.01
-32
32
0.01
-16
16
0.01
-8
8
0.01
-4
4
mA
mA
mA
TIMING REQUREMENTS AND SWITCHING CHARACTERISTICS
LVC
5V
LVC
3.3V
LVC
2.5V
LVC
1.8V
PARAMETER
INPUT
OUTPUT
MAX or MIN
fmax
MIN
MIN
200
2
2
1.1
1
0.5
4.1
4.1
4.4
4.4
4.1
4.1
175
2.7
2.7
1.3
1.2
1.2
5.9
5.9
6.2
6.2
5.9
5.9
175
2.7
2.7
1.7
1.4
0.3
7.1
7.1
7.7
7.7
7
80
6.2
6.2
2.9
1.9
CLK
PRE or CLR low
Data
tw
tsu
MIN
PRE or CLR inactive
th
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
MIN
0
13.4
13.4
14.4
14.4
12.9
12.9
CLK
CLK
Q
Q
MAX
MAX
MAX
PRE or CLR
Q or Q
7
UNIT:ns
127
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.