SN65MLVD2
SN65MLVD3
www.ti.com
SLLS767–NOVEMBER 2006
INPUTS
- V
CLOCK INPUT
V
V
CM
A
B
V
- V
B
A
0.4 V
1.0 V
1/fo
Period Jitter
IDEAL
OUTPUT
V
OH
V
/2
CC
V
OL
V
1/fo
A
PRBS INPUT
V
ACTUAL
OUTPUT
OH
/2
V
B
V
CC
V
Peak to Peak Jitter
OL
V
OH
/2
t
c(n)
OUTPUT
V
CC
t
= | t
c(n)
- 1/fo |
jit(per)
V
OL
t
jit(pp)
Cycle to Cycle Jitter
V
OH
/2
OUTPUT
V
CC
V
OL
t
c(n)
t
c(n+1)
t
= | t
- t
|
jit(cc)
c(n) c(n+1)
A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.
B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software
C. Period jitter is measured using a 125-MHz 50 ± 1% duty cycle clock input.
D. Deterministic jitter and random jitter are measured using a 250-Mbps 215-1 PRBS input
Figure 4. Receiver Jitter Measurement Waveforms
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