SLLS771A – NOVEMBER 2006 – REVISED DECEMBER 2006
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION
PART NUMBER
SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
(1)
(2)
DGS, DGSR
(2)
PACKAGE
(1)
MARKED AS
BTT
BTU
BTF
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at
The R suffix indicated tape and reel.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
CC
V
(A)
, V
(B)
, V
(Y)
, V
(Z)
V
(TRANS)
V
I
P
D
T
J
(1)
(2)
Supply voltage
range
(2)
–0.3 V to 7 V
–9 V to 14 V
–50 to 50 V
-0.3 V to V
CC
+0.3 V
See the dissipation rating table
170°C
Voltage range at any bus terminal (A, B, Y, Z)
Voltage input, transient pulse through 100
Ω.
See
(A, B, Y, Z)
Input voltage range (D, DE, RE)
Continuous total power dissipation
Junction temperature
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
POWER DISSIPATION RATINGS
PACKAGE
DGS-10
(1)
T
A
< 25°C
463 mW
DERATING FACTOR
(1)
ABOVE T
A
< 25°C
3.71 mW/°C
T
A
= 85°C
241 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
Human Body Model
(1)
Field-induced-Charged Device Mode
(2)
Machine Model
(1)
(2)
All pins
All pins
TEST CONDITIONS
A,B,Y,Z, and GND
MIN
TYP
16k
6k
1.5k
200
MAX
UNIT
V
V
V
V
Tested in accordance JEDEC Standard 22, Test Method A114-A. Bus pin stressed with respect to a common connection of GND and
V
CC
.
Tested in accordance JEDEC Standard 22, Test Method C101.
2
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