SN65HVD3080E
SN65HVD3083E
SN65HVD3086E
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SLLS771A–NOVEMBER 2006–REVISED DECEMBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
Y
3 V
V
S1
O
D
3 V
1.5 V
1.5 V
Z
V
I
DE
0 V
0.5 V
R
= 110 W
t
L
PZH
C
= 50 pF
L
±1%
VOH
Input
Generator
±20%
50 W
V
I
V
2.5 V
O
» 0 V
t
Generator: PRR = 500 kHz,
50% Duty Cycle, t < 6 ns,
C
Includes Fixture and
PHZ
L
Instrumentation Capacitance
r
t < 6 ns, Z = 50 W
f
O
Figure 5. Driver High-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
3 V
R
= 110 W
3 V
L
±1%
Y
Z
1.5 V
1.5 V
S1
D
V
V
0 V
I
O
t
0 V
5 V
PZL
DE
50 W
t
PLZ
C
= 50 pF
L
Input
V
V
O
±20%
0.5 V
Generator
I
2.5 V
V
OL
Generator: PRR = 500 kHz,
50% Duty Cycle, t < 6 ns,
C
Includes Fixture and
L
Instrumentation Capacitance
r
t < 6 ns, Z = 50 W
f
O
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
I
A
B
A
I
O
R
V
A
V
ID
V
IC
V
O
I
B
V
A
+ V
B
V
B
2
Figure 7. Receiver Voltage and Current Definitions
A
3 V
0 V
V
O
R
Input
1.5 V
1.5 V
V
I
V
I
50 Ω
Generator
B
1.5 V
C
= 15 pF
L
t
t
PHL
PLH
RE
±20%
V
OH
OL
90% 90%
1.5 V
10%
1.5 V
10%
V
Generator: PRR = 500 kHz,
50% Duty Cycle,t < 6 ns,
O
V
CL Includes Fixture and
r
t
t
f
Instrumentation Capacitance
r
t < 6 ns, Z = 50 W
f
O
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
7
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