Introduction
Table 2−2. Signal Descriptions
†
(Continued)
PIN
NO.
NAME
172-PIN
HFG
131
I/O/Z‡
PU/PD§
DESCRIPTION
TESTSEL
I
PD
Test Pin. Reserved for TI. Must be connected to ground.
Device Reset (in) and Watchdog Reset (out).
Device reset. XRS causes the device to terminate execution. The PC points to
the address contained at the location 0x3FFFC0. When XRS is brought to a high
level, execution begins at the location pointed to by the PC. This pin is driven low
by the DSP when a watchdog reset occurs. During watchdog reset, the XRS pin
is driven low for the watchdog reset duration of 512 XCLKIN cycles.
The output buffer of this pin is an open-drain with an internal pullup (100
µA,
typical). It is recommended that this pin be driven by an open-drain device.
XRS
156
I/O
PU
TEST1
TEST2
66
65
I/O
I/O
−
−
Test Pin. Reserved for TI. On F281x devices, TEST1 must be left unconnected.
Test Pin. Reserved for TI. On F281x devices, TEST2 must be left unconnected.
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan
system control of the operations of the device. If this signal is not connected or
driven low, the device operates in its functional mode, and the test reset signals
are ignored.
TRST
132
I
PD
NOTE: Do not use pullup resistors on TRST; it has an internal pulldown device.
In a low-noise environment, TRST can be left floating. In a high-noise
environment, an additional pulldown resistor may be needed. The value of this
resistor should be based on drive strength of the debugger pods applicable to
the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is
application specific, it is recommended that each target board is validated for
proper operation of the debugger and the application.
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal pullup. This serial control input is
clocked into the TAP controller on the rising edge of TCK.
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected
register (instruction or data) on a rising edge of TCK.
JTAG scan out, test data output (TDO). The contents of the selected register
(instruction or data) is shifted out of TDO on the falling edge of TCK.
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to
or from the emulator system and is defined as input/output through the
JTAG scan.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to
or from the emulator system and is defined as input/output through the
JTAG scan.
TCK
TMS
TDI
TDO
133
123
128
124
I
I
I
O/Z
PU
PU
PU
−
EMU0
133
I/O/Z
PU
EMU1
143
I/O/Z
PU
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
December 2004 − Revised September 2006
SGUS053B
9
TI [ TEXAS INSTRUMENTS ]
