SMJ320F2812 参数 Datasheet PDF下载

Introduction

Table 2−2. Signal Descriptions

†

(Continued)

PIN

NO.

NAME

172-PIN

HFG

I/O/Z‡

PU/PD§

DESCRIPTION

ADC ANALOG INPUT SIGNALS

ADCINA7

ADCINA6

ADCINA5

ADCINA4

ADCINA3

ADCINA2

ADCINA1

ADCINA0

ADCINB7

ADCINB6

ADCINB5

ADCINB4

ADCINB3

ADCINB2

ADCINB1

ADCINB0

163

164

165

166

167

168

169

170

9

8

7

6

5

4

3

2

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

ADC Voltage Reference Output (2 V). Requires a low ESR (50 mΩ − 1.5

Ω)

ceramic bypass capacitor of 10

µF

to analog ground. (Can accept external

reference input (2 V) if the software bit is enabled for this mode. 1-µF to 10-µF

low ESR capacitor can be used in the external reference mode.)

ADC Voltage Reference Output (1 V). Requires a low ESR (50 mΩ − 1.5

Ω)

ceramic bypass capacitor of 10

µF

to analog ground. (Can accept external

reference input (1 V) if the software bit is enabled for this mode. 1-µF to 10-µF

low ESR capacitor can be used in the external reference mode.)

ADC External Current Bias Resistor (24.9 kΩ

±5%)

Test Pin. Reserved for TI. Must be left unconnected.

ADC Analog GND

ADC Analog Power (3.3 V)

Common Low Side Analog Input. Connect to analog ground.

ADC Analog GND

ADC Analog GND

ADC Analog 3.3-V Supply

ADC Analog 3.3-V Supply

ADC Digital GND

ADC Digital 1.8-V (or 1.9-V) Supply

3.3-V Analog I/O Power Pin

Eight-channel analog inputs for Sample-and-Hold B. The ADC pins should not

be driven before the VDDA1, VDDA2, and VDDAIO pins have been fully powered

up.

Eight-channel analog inputs for Sample-and-Hold A. The ADC pins should not

be driven before VDDA1, VDDA2, and VDDAIO pins have been fully powered up.

ADCREFP

11

O

ADCREFM

10

O

ADCRESEXT

ADCBGREFIN

AVSSREFBG

AVDDREFBG

ADCLO

VSSA1

VSSA2

VDDA1

VDDA2

VSS1

VDD1

VDDAIO

16

160

12

13

171

15

161

14

162

159

158

1

O

I

I

I

I

I

I

I

I

I

I

VSSAIO

172

Analog I/O Ground Pin

† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.

‡ I = Input, O = Output, Z = High impedance

§ PU = pin has internal pullup; PD = pin has internal pulldown

10

SGUS053B

December 2004 − Revised September 2006