Introduction
Table 2−2. Signal Descriptions
†
(Continued)
PIN
NO.
NAME
172-PIN
HFG
I/O/Z‡
PU/PD§
DESCRIPTION
XINTF SIGNALS (CONTINUED)
Microprocessor/Microcomputer
Mode
Select.
Switches
between
microprocessor and microcomputer mode. When high, Zone 7 is enabled on the
external interface. When low, Zone 7 is disabled from the external interface and
on-chip boot ROM may be accessed instead. This signal is latched into the
XINTCNF2 register on a reset and the user can modify this bit in software. The
state of the XMP/MC pin is ignored after reset.
External Hold Request. XHOLD, when active (low), requests the XINTF to
release the external bus and place all buses and strobes into a high-impedance
state. The XINTF releases the bus when any current access is complete and
there are no pending accesses on the XINTF.
External Hold Acknowledge. XHOLDA is driven active (low) when the XINTF has
granted a XHOLD request. All XINTF buses and strobe signals are in a
high-impedance state. XHOLDA is released when the XHOLD signal is
released. External devices should only drive the external bus when XHOLDA is
active (low).
XINTF Zone 0 and Zone 1 Chip Select. XZCS0AND1 is active (low) when an
access to the XINTF Zone 0 or Zone 1 is performed.
XINTF Zone 2 Chip Select. XZCS2 is active (low) when an access to the XINTF
Zone 2 is performed.
XINTF Zone 6 and Zone 7 Chip Select. XZCS6AND7 is active (low) when an
access to the XINTF Zone 6 or Zone 7 is performed.
Write Enable. Active-low write strobe. The write strobe waveform is specified,
per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.
Read Enable. Active-low read strobe. The read strobe waveform is specified,
per zone basis, by the Lead, Active, and Trail periods in the XTIMINGx registers.
NOTE: The XRD and XWE signals are mutually exclusive.
Read Not Write Strobe. Normally held high. When low, XR/W indicates write
cycle is active; when high, XR/W indicates read cycle is active.
Ready Signal. Indicates peripheral is ready to complete the access when
asserted to 1. XREADY can be configured to be a synchronous or an
asynchronous input. See the timing diagrams for more details.
XMP/MC
17
I
PD
XHOLD
155
I
PU
XHOLDA
80
O/Z
−
XZCS0AND1
XZCS2
XZCS6AND7
XWE
43
86
130
82
O/Z
O/Z
O/Z
O/Z
−
−
−
−
XRD
41
O/Z
−
XR/W
50
O/Z
−
XREADY
157
I
PU
JTAG AND MISCELLANEOUS SIGNALS
Oscillator Input − input to the internal oscillator. This pin is also used to feed an
external clock. The 28x can be operated with an external clock source, provided
that the proper voltage levels be driven on the X1/XCLKIN pin. It should be noted
that the X1/XCLKIN pin is referenced to the 1.8-V (or 1.9-V) core digital power
supply (VDD), rather than the 3.3-V I/O supply (VDDIO). A clamping diode may
be used to clamp a buffered clock signal to ensure that the logic-high level does
not exceed VDD (1.8 V or 1.9 V) or a 1.8-V oscillator may be used.
Oscillator Output
Output clock derived from SYSCLKOUT to be used for external wait-state
generation and as a general-purpose clock source. XCLKOUT is either the
same frequency, 1/2 the frequency, or 1/4 the frequency of SYSCLKOUT. At
reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by
setting bit 3 (CLKOFF) of the XINTCNF2 register to 1.
X1/XCLKIN
75
I
X2
74
O
XCLKOUT
117
O
−
† Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
‡ I = Input, O = Output, Z = High impedance
§ PU = pin has internal pullup; PD = pin has internal pulldown
8
SGUS053B
December 2004 − Revised September 2006
TI [ TEXAS INSTRUMENTS ]
