SPNS174
–
SEPTEMBER 2011
4.13 On-Chip SRAM Initialization and Testing
4.13.1 On-Chip SRAM Self-Test Using PBIST
4.13.1.1 Features
•
•
•
Extensive instruction set to support various memory test algorithms
ROM-based algorithms allow application to run TI production-level memory tests
Independent testing of all on-chip SRAM
4.13.1.2 PBIST RAM Groups
Table 4-25. PBIST RAM Grouping
Test Pattern (Algorithm)
Memory
RAM Group
Test Clock
MEM Type
triple read
slow read
ALGO MASK
0x1
PBIST_ROM
STC_ROM
DCAN1
DCAN2
DCAN3
ESRAM1
MIBSPI1
MIBSPI3
MIBSPI5
VIM
MIBADC1
DMA
N2HET1
HET TU1
RTP
MIBADC2
N2HET2
HET TU2
ESRAM5
ESRAM6
ETHERNET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
18
19
20
21
22
23
24
25
USB
ESRAM8
(1)
26
27
28
VCLK3
HCLK
VCLK3
ROM CLK
ROM CLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
VCLK
VCLK
HCLK
VCLK
VCLK
HCLK
VCLK
VCLK
VCLK
HCLK
HCLK
ROM
ROM
Dual Port
Dual Port
Dual Port
Single Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Dual Port
Single Port
Single Port
Dual Port
Single Port
Dual Port
Single Port
Single Port
4240
66600
266280
8700
6360
133160
33440
33440
33440
12560
4200
18960
31680
6480
37800
4200
31680
6480
266280
266280
X
X
triple read
fast read
ALGO MASK
0x2
X
X
25200
25200
25200
266280
March 13N
(1)
two port
(cycles)
ALGO MASK
0x4
March 13N
(1)
single port
(cycles)
ALGO MASK
0x8
PRODUCT PREVIEW
82
There are several memory testing algorithms stored in the PBIST ROM. However, TI recommends the March13N algorithm for
application testing.
The PBIST ROM clock frequency is limited to 100MHz, if 100MHz
<
HCLK
<=
HCLKmax, or HCLK, if
HCLK
<=
100MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
System Information and Electrical Specifications
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©
2011, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
