RM48L550PGET 参数 Datasheet PDF下载

SPNS174

–

SEPTEMBER 2011

The parity protection for peripheral RAMs is not enabled by default and must be enabled by the

application. Each individual peripheral contains control registers to enable the parity protection for

accesses to its RAM.

NOTE

The CPU read access gets the actual data from the peripheral. The application can choose

to generate an interrupt whenever a peripheral RAM parity error is detected.

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2011, Texas Instruments Incorporated

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