SPNS174
–
SEPTEMBER 2011
4.9.3
Master/Slave Access Privileges
The table below lists the access permissions for each bus master on the device. A bus master is a module
that can initiate a read or a write transaction on the device.
Each slave module on the main interconnect is listed in the table. A "Yes" indicates that the module listed
in the "MASTERS" column can access that slave module.
Table 4-22. Master / Slave Access Matrix
MASTERS
ACCESS MODE
Flash Module
Bus2 Interface:
OTP, ECC,
EEPROM Bank
SLAVES ON MAIN SCR
Non-CPU
Accesses to
Program Flash
and CPU Data
RAM
CRC
EMIF, Ethernet,
USB Slave
Interfaces
Peripheral
Control
Registers, All
Peripheral
Memories, And
All System
Module Control
Registers And
Memories
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
CPU READ
CPU WRITE
DMA
POM
DMM
DAP
HTU1
HTU2
EMAC
OHCI
User/Privilege
User/Privilege
User
User
User
Privilege
Privilege
Privilege
User
User
Yes
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
4.9.3.1
Special Notes on Accesses to Certain Slaves
Write accesses to the Power Domain Management Module (PMM) control registers are limited to the CPU
(master id = 1). The other masters can only read from these registers.
A debugger can also write to the PMM registers. The master-id check is disabled in debug mode.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned OFF.
Copyright
©
2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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