RM48L950
RM48L750
RM48L550
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SPNS174–SEPTEMBER 2011
4.9.2 Memory Map Table
Please refer to and for a block diagrams showing the devices interconnect.
Table 4-21. Device Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
SIZE L SIZE
MODULE NAME
START
END
Memories tightly coupled to the ARM Cortex-R4F CPU
2MB/
3MB
TCM Flash
CS0
0x0000_0000
0x0800_0000
0x2000_0000
0x00FF_FFFF
0x0BFF_FFFF
0x20FF_FFFF
16MB
64MB
16MB
TCM RAM + RAM
ECC
CSRAM0
256KB
Abort
Flash mirror
frame
Mirrored Flash
3MB
External Memory Accesses
EMIF Chip Select
2 (asynchronous)
EMIF select 2
EMIF select 3
EMIF select 4
EMIF select 0
0x6000_0000
0x6400_0000
0x6800_0000
0x8000_0000
0x63FF_FFFF
0x67FF_FFFF
0x6BFF_FFFF
0x87FF_FFFF
64MB
16MB
16MB
16MB
EMIF Chip Select
3 (asynchronous)
64MB
64MB
Access to "Reserved" space will
generate Abort
EMIF Chip Select
4 (asynchronous)
EMIF Chip Select
0 (synchronous)
128MB 128MB
Flash Module Bus2 Interface
Customer OTP,
TCM Flash Banks
0xF000_0000
0xF000_FFFF
0xF000_FFFF
64KB
16KB
4KB
Customer OTP,
EEPROM Bank
0xF000_E000
0xF004_0000
8KB
8KB
Customer
OTP–ECC, TCM
Flash Banks
0xF004_1FFF
0xF004_1FFF
2KB
1KB
Customer
OTP–ECC,
0xF004_1C00
1KB
EEPROM Bank
TI OTP, TCM
Flash Banks
0xF008_0000
0xF008_E000
0xF00C_0000
0xF00C_1C00
0xF008_FFFF
0xF008_FFFF
0xF00C_1FFF
0xF00C_1FFF
64KB
8KB
8KB
1KB
16KB
4KB
2KB
1KB
Abort
TI OTP, EEPROM
Bank
TI OTP–ECC,
TCM Flash Banks
TI OTP–ECC,
EEPROM Bank
EEPROM
Bank–ECC
0xF010_0000
0xF020_0000
0xF040_0000
0xF013_FFFF
0xF03F_FFFF
0xF04F_FFFF
256KB
2MB
8KB
64KB
384KB
EEPROM Bank
Flash Data Space
ECC
1MB
Ethernet and EMIF slave interfaces
CPPI Memory
Slave (Ethernet
RAM)
0xFC52_0000
0xFCF7_8000
0xFC52_1FFF
0xFCF7_87FF
8KB
2KB
8KB
2KB
Abort
CPGMAC Slave
(Ethernet Slave)
No error
CPGMACSS
Wrapper
(Ethernet
Wrapper)
0xFCF7_8800
0xFCF7_88FF
256B
256B
No error
Copyright © 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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