RM48L950
RM48L750
RM48L550
SPNS174–SEPTEMBER 2011
www.ti.com
Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
L SIZE
START
END
W2FC (USB
device controller
registers)
0xFCF7_8A00
0xFCF7_8A7F
128B
128B
Abort
OHCI (USB Host
controller
0xFCF7_8B00
0xFCFF_E800
0xFCF7_8BFF
0xFCFF_E8FF
256B
256B
256B
256B
Abort
Abort
registers)
EMIF Registers
CRC
Cyclic Redundancy Checker (CRC) Module Registers
CRC frame
0xFE00_0000
0xFEFF_FFFF
Peripheral Memories
0xFF0B_FFFF
16MB
512B
Accesses above 0x200 generate abort.
MIBSPI5 RAM
MIBSPI3 RAM
MIBSPI1 RAM
PCS[5]
PCS[6]
PCS[7]
0xFF0A_0000
0xFF0C_0000
0xFF0E_0000
128KB
128KB
128KB
2KB
2KB
2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
Abort for accesses above 2KB
0xFF0D_FFFF
0xFF0F_FFFF
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
DCAN3 RAM
DCAN2 RAM
DCAN1 RAM
MIBADC2 RAM
MIBADC1 RAM
N2HET2 RAM
N2HET1 RAM
PCS[13]
PCS[14]
PCS[15]
PCS[29]
PCS[31]
PCS[34]
PCS[35]
0xFF1A_0000
0xFF1C_0000
0xFF1E_0000
0xFF3A_0000
0xFF3E_0000
0xFF44_0000
0xFF46_0000
0xFF1B_FFFF
0xFF1D_FFFF
0xFF1F_FFFF
0xFF3B_FFFF
0xFF3F_FFFF
0xFF45_FFFF
128KB
128KB
128KB
128KB
128KB
128KB
128KB
2KB
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
2KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
8KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
16KB
16KB
Wrap around for accesses to
unimplemented address offsets lower
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
0xFF47_FFFF
0xFF4D_FFFF
N2HET2 TU2
RAM
PCS[38]
PCS[39]
0xFF4C_0000
0xFF4E_0000
128KB
128KB
1KB
1KB
Abort
Abort
N2HET1 TU1
RAM
0xFF4F_FFFF
Debug Components
0xFFA0_0FFF
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
CSCS1
CSCS2
0xFFA0_0000
0xFFA0_1000
0xFFA0_2000
4KB
4KB
4KB
4KB
4KB
4KB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
0xFFA0_1FFF
0xFFA0_2FFF
Reads return zeros, writes have no
effect
ETM-R4
Reads return zeros, writes have no
effect
CoreSight TPIU
POM
CSCS3
CSCS4
0xFFA0_3000
0xFFA0_4000
0xFFA0_3FFF
0xFFA0_4FFF
4KB
4KB
4KB
4KB
Abort
Peripheral Control Registers
72
System Information and Electrical Specifications
Copyright © 2011, Texas Instruments Incorporated
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