SPNS174
–
SEPTEMBER 2011
2.4.2
2.4.2.1
ZWT Package
Multi-Buffered Analog-to-Digital Converters (MibADC)
Table 2-24. ZWT Multi-Buffered Analog-to-Digital Converters (MibADC1, MibADC2)
Terminal
Signal Name
337
ZWT
V15
V16
W15
V19
W16
W18
W19
Signal
Type
Input
Input
Power
Ground
-
-
Default
Pull State
-
Pull Type
Description
ADREFHI
(1)
ADREFLO
(1)
VCCAD
VSSAD
(1)
-
ADC high reference
supply
ADC low reference supply
Operating supply for ADC
ADC supply power
AD1EVT/MII_RX_ER
MIBSPI3NCS[0]/AD2EVT/GIOB[2]
AD1IN[0]
AD1IN[01]
AD1IN[02]
AD1IN[03]
AD1IN[04]
AD1IN[05]
AD1IN[06]
AD1IN[07]
AD1IN[08]
/ AD2IN[08]
AD1IN[09]
/ AD2IN[09]
AD1IN[10]
/ AD2IN[10]
AD1IN[11]
/ AD2IN[11]
AD1IN[12]
/ AD2IN[12]
AD1IN[13]
/ AD2IN[13]
AD1IN[14]
/ AD2IN[14]
AD1IN[15]
/ AD2IN[15]
AD1IN[16]
/ AD2IN[0]
AD1IN[17]
/ AD2IN[01]
AD1IN[18]
/ AD2IN[02]
AD1IN[19]
/ AD2IN[03]
AD1IN[20]
/ AD2IN[04]
AD1IN[21]
/ AD2IN[05]
AD1IN[22]
/ AD2IN[06]
AD1IN[23]
/ AD2IN[07]
(1)
N19
V10
W14
V17
V18
T17
U18
R17
T19
V14
P18
W17
U17
U19
T16
T18
R18
P19
V13
U13
U14
U16
U15
T15
R19
R16
Input
I/O
Input
Pull Down
Pull Up
-
Programmable,
20uA
Programmable,
20uA
-
ADC1 event trigger input,
or GIO
ADC2 event trigger input,
or GIO
ADC1 analog input
Input
-
-
ADC1/ADC2 shared
analog inputs
The ADREFHI, ADREFLO, VCCAD and VSSAD connections are common for both ADC cores.
Copyright
©
2011, Texas Instruments Incorporated
Device Package and Terminal Functions
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