SPNS174
–
SEPTEMBER 2011
Table 4-36. Reset/Abort/Error Sources (continued)
ERROR SOURCE
SYSTEM MODE
eFuse Controller
eFuse Controller error
eFuse Controller - Any bit set in the error status register
eFuse Controller self-test error
WWD Non-Maskable Interrupt exception
Power-Up Reset
Oscillator fail / PLL slip
Watchdog exception
CPU Reset (driven by the CPU STC)
Software Reset
External Reset
(2)
(2)
ERROR RESPONSE
ESM HOOKUP
group.channel
3.1
1.40
1.41
2.24
n/a
n/a
n/a
n/a
n/a
n/a
User/Privilege
User/Privilege
User/Privilege
WINDOWED WATCHDOG
n/a
ERRORS REFLECTED IN THE SYSESR REGISTER
n/a
n/a
n/a
n/a
n/a
n/a
ESM
ESM
ESM
ESM
Reset
Reset
Reset
Reset
Reset
Reset
Oscillator fail/PLL slip can be configured in the system register (SYS.PLLCTL1) to generate a reset.
This device includes a digital windowed watchdog (DWWD) module that protects against runaway code
execution.
The DWWD module allows the application to configure the time window within which the DWWD module
expects the application to service the watchdog. A watchdog violation occurs if the application services the
watchdog outside of this window, or fails to service the watchdog at all. The application can choose to
generate a system reset or a non-maskable interrupt to the CPU in case of a watchdog violation.
The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog
can only be disabled upon a system reset.
Copyright
©
2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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