SPNS174
–
SEPTEMBER 2011
4.19 Reset / Abort / Error Sources
Table 4-36. Reset/Abort/Error Sources
ERROR SOURCE
SYSTEM MODE
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Illegal instruction
MPU access violation
B0 TCM (even) ECC single error (correctable)
B0 TCM (even) ECC double error (non-correctable)
B0 TCM (even) uncorrectable error (i.e. redundant address
decode)
B0 TCM (even) address bus parity error
B1 TCM (odd) ECC single error (correctable)
B1 TCM (odd) ECC double error (non-correctable)
B1 TCM (odd) uncorrectable error (i.e. redundant address
decode)
B1 TCM (odd) address bus parity error
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to EEPROM bank)
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank
accesses)
FMC uncorrectable error - address parity error on Bus1
accesses
FMC correctable error - Accesses to EEPROM bank
FMC uncorrectable error - Accesses to EEPROM bank
External imprecise error on read (Illegal transaction with ok
response)
External imprecise error on write (Illegal transaction with ok
response)
Memory access permission violation
Memory parity error
External imprecise error on read (Illegal transaction with ok
response)
External imprecise error on write (Illegal transaction with ok
response)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
(1)
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SRAM
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FLASH
User/Privilege
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DMA TRANSACTIONS
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DMM TRANSACTIONS
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HET TU1 (HTU1)
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Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
ESM
ESM
1.5
1.13
ESM
ESM
ESM
ESM
1.5
1.13
1.2
1.3
ESM
Abort (CPU), ESM =>
nERROR
ESM => nERROR
ESM => NMI
ESM
ESM
1.6
3.7
3.7
2.4
1.35
1.36
ESM
Abort (CPU), ESM =>
nERROR
ESM => NMI
ESM => NMI
ESM
Abort (CPU), ESM =>
nERROR
ESM => NMI
ESM => NMI
1.26
3.3
2.6
2.10
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
Undefined Instruction Trap
(CPU)
(1)
Abort (CPU)
n/a
n/a
n/a
n/a
n/a
ERROR RESPONSE
ESM HOOKUP
group.channel
3.5
2.8
2.12
The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
System Information and Electrical Specifications
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2011, Texas Instruments Incorporated
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