SPNS174
–
SEPTEMBER 2011
Table 4-36. Reset/Abort/Error Sources (continued)
ERROR SOURCE
Memory parity error
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
Memory parity error
Memory parity error
Memory parity error
Any error reported by slave being accessed
Any error reported by slave being accessed
MibSPI1 memory parity error
MibSPI3 memory parity error
MibSPI5 memory parity error
MibADC1 Memory parity error
MibADC2 Memory parity error
DCAN1 memory parity error
DCAN2 memory parity error
DCAN3 memory parity error
PLL slip error
PLL #2 slip error
Clock monitor interrupt
DCC1 error
DCC2 error
Self test failure
Compare failure
Memory parity error
VMON out of voltage range
CPU Selftest (LBIST) error
Mux configuration error
PSCON compare error
PSCON self-test error
104
SYSTEM MODE
User/Privilege
HET TU2 (HTU2)
User/Privilege
User/Privilege
User/Privilege
User/Privilege
N2HET1
User/Privilege
N2HET2
User/Privilege
ETHERNET MASTER INTERFACE
User/Privilege
User/Privilege
MIBSPI
User/Privilege
User/Privilege
User/Privilege
MIBADC
User/Privilege
User/Privilege
DCAN
User/Privilege
User/Privilege
User/Privilege
PLL
User/Privilege
User/Privilege
CLOCK MONITOR
User/Privilege
DCC
User/Privilege
User/Privilege
CCM-R4
User/Privilege
User/Privilege
VIM
User/Privilege
VOLTAGE MONITOR
n/a
CPU SELFTEST (LBIST)
User/Privilege
PIN MULTIPLEXING CONTROL
User/Privilege
POWER DOMAIN CONTROL
User/Privilege
User/Privilege
ESM
ESM
1.38
1.39
ESM
1.37
ESM
1.27
Reset
n/a
ESM
1.15
ESM
ESM => NMI
1.31
2.2
ESM
ESM
1.30
1.62
ESM
1.11
ESM
ESM
1.10
1.42
ESM
ESM
ESM
1.21
1.23
1.22
ESM
ESM
1.19
1.1
ESM
ESM
ESM
1.17
1.18
1.24
ESM
ESM
1.43
1.44
USB HOST CONTROLLER (OHCI) MASTER INTERFACE
ESM
1.7
ESM
1.7
Interrupt => VIM
Interrupt => VIM
ESM
ESM
n/a
n/a
1.9
1.8
ERROR RESPONSE
ESM
ESM HOOKUP
group.channel
1.8
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2011, Texas Instruments Incorporated