RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
3.3 Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter
Description
Conditions
Pipeline mode
Max
Unit
fHCLK
HCLK - System clock frequency
200
MHz
enabled
Pipeline mode
disabled
50
MHz
fGCLK
fVCLK
GCLK - CPU clock frequency
fHCLK
100
MHz
MHz
MHz
VCLK - Primary peripheral clock frequency
fVCLK2
VCLK2 - Secondary peripheral clock
frequency
100
fVCLK3
VCLK3 - Secondary peripheral clock
frequency
100
100
100
100
100
fVCLK
MHz
MHz
MHz
MHz
MHz
MHz
fVCLKA1
fVCLKA2
fVCLKA3
fVCLKA4
fRTICLK
VCLKA1 - Primary asynchronous
peripheral clock frequency
VCLKA2 - Secondary asynchronous
peripheral clock frequency
VCLKA3 - Primary asynchronous
peripheral clock frequency
VCLKA4 - Secondary asynchronous
peripheral clock frequency
RTICLK - clock frequency
3.4 Wait States Required
RAM
0
0
Address Waitstates
0MHz
200MHz
Data Waitstates
0MHz
200MHz
Flash
1
Address Waitstates
0
120MHz
200MHz
200MHz
0MHz
Data Waitstates
0
1
2
3
0MHz
50MHz
100MHz
150MHz
Figure 3-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50MHz in non-pipelined
mode. The flash supports a maximum CPU clock speed of 200MHz in pipelined mode with one address wait
state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright © 2012, Texas Instruments Incorporated
Device Operating Conditions
47
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