RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
www.ti.com
4.21 Debug Subsystem
4.21.1 Block Diagram
The device contains an ICEPICK module to allow JTAG access to the scan chains.
Boundary Scan
Boundary Scan I/F
BSR/BSDL
Debug
ROM1
TRST
TMS
TCK
RTCK
Debug APB
TDI
DAP
TDO
Secondary Tap 0
APB Mux
AHB-AP
APB slave
Cortex
R4F
POM
from
to SCR1 via A2A
PCR1/Bridge
Secondary Tap 2
Test Tap 0
AJSM
eFuse Farm
PSCON
Test Tap 1
Figure 4-20. Debug Subsystem Block Diagram
4.21.2 Debug Components Memory Map
Table 4-38. Debug Components Memory Map
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
UNIMPLEMENTED LOCATIONS IN
FRAME
FRAME CHIP
SELECT
FRAME ACTUA
MODULE NAME
SIZE
4kB
4kB
L SIZE
START
END
CoreSight Debug
ROM
Reads return zeros, writes have no
effect
CSCS0
CSCS1
0xFFA0_0000
0xFFA0_0FFF
4kB
Cortex-R4F
Debug
Reads return zeros, writes have no
effect
0xFFA0_1000
0xFFA0_1FFF
4kB
4.21.3 JTAG Identification Code
The JTAG ID code for this device is 0x0B95502F. This is the same as the device ICEPick Identification
Code.
4.21.4 Debug ROM
The Debug ROM stores the location of the components on the Debug APB bus:
112
System Information and Electrical Specifications
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