RM46L450
RM46L850
SPNS184 –SEPTEMBER 2012
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4.19 Reset / Abort / Error Sources
Table 4-37. Reset/Abort/Error Sources
ESM HOOKUP
group.channel
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
CPU TRANSACTIONS
User/Privilege
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
n/a
n/a
n/a
User/Privilege
User/Privilege
Undefined Instruction Trap
(CPU)(1)
Illegal instruction
User/Privilege
n/a
n/a
MPU access violation
User/Privilege
SRAM
Abort (CPU)
B0 TCM (even) ECC single error (correctable)
User/Privilege
ESM
1.26
3.3
Abort (CPU), ESM =>
nERROR
B0 TCM (even) ECC double error (non-correctable)
User/Privilege
User/Privilege
B0 TCM (even) uncorrectable error (i.e. redundant address
decode)
ESM => NMI => nERROR
2.6
B0 TCM (even) address bus parity error
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM
2.10
1.28
B1 TCM (odd) ECC single error (correctable)
Abort (CPU), ESM =>
nERROR
B1 TCM (odd) ECC double error (non-correctable)
User/Privilege
3.5
B1 TCM (odd) uncorrectable error (i.e. redundant address
decode)
User/Privilege
User/Privilege
ESM => NMI => nERROR
ESM => NMI => nERROR
2.8
B1 TCM (odd) address bus parity error
2.12
FLASH WITH CPU BASED ECC
FMC correctable error - Bus1 and Bus2 interfaces (does not
include accesses to Bank 7)
User/Privilege
User/Privilege
User/Privilege
ESM
1.6
3.7
2.4
FMC uncorrectable error - Bus1 and Bus2 accesses
(does not include address parity error)
Abort (CPU), ESM =>
nERROR
FMC uncorrectable error - address parity error on Bus1
accesses
ESM => NMI => nERROR
FMC correctable error - Accesses to Bank 7
FMC uncorrectable error - Accesses to Bank 7
User/Privilege
User/Privilege
ESM
ESM
1.35
1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
User/Privilege
ESM
ESM
1.5
External imprecise error on write (Illegal transaction with ok
response)
1.13
Memory access permission violation
Memory parity error
User/Privilege
User/Privilege
ESM
ESM
1.2
1.3
HET TU1 (HTU1)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
Memory parity error
ESM
HET TU2 (HTU2)
NCNB (Strongly Ordered) transaction with slave error response
External imprecise error (Illegal transaction with ok response)
Memory access permission violation
User/Privilege
User/Privilege
User/Privilege
User/Privilege
Interrupt => VIM
Interrupt => VIM
ESM
n/a
n/a
1.9
1.8
Memory parity error
ESM
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
108
System Information and Electrical Specifications
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