RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
RM46Lx50 16/32-Bit RISC Flash Microcontroller
1 RM46Lx50 16/32-Bit RISC Flash Microcontroller
1.1 Features
1
• High-Performance Microcontroller for Safety
Critical Applications
• Two High-End Timer Modules (N2HET)
– N2HET1: 32 programmable channels
– Dual CPUs running in lockstep
– ECC on flash and RAM interfaces
– Built-In Self Test for CPU and on-chip RAMs
– Error Signaling Module with Error Pin
– Voltage and Clock Monitoring
– N2HET2: 18 programmable channels
– 160 Word Instruction RAM with parity
protection each
– Each includes Hardware Angle Generator
– Dedicated Transfer Units (HTU) on N2HETs
• Two 10/12-bit Multi-Buffered ADC Modules
– ADC1: 24 channels
– ADC2: 16 channels
– 16 shared channels
– 64 result buffers with parity protection each
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
• ARM® Cortex™ – R4F 32-bit RISC CPU
– 1.66DMIPS/MHz with 8-stage pipeline
– FPU with Single/Double Precision
– 12-Region Memory Protection Unit
– Open Architecture with 3rd Party Support
• Operating Conditions
– 200MHz System Clock
– Core Supply Voltage (VCC): 1.14V - 1.32V
– I/O Supply Voltage (VCCIO): 3.0V - 3.6V
• Integrated Memory
•
•
IEEE 802.3 compliant (3.3V-I/O only)
Supports MII, RMII and MDIO
– USB (revision 2.0 full-speed)
– Up to 1.25MB Program Flash with ECC
– Up to 192KB RAM with ECC
– 64KB Flash for emulated EEPROM with ECC
• 16- bit External Memory Interface (EMIF)
• Common Platform Architecture
•
2-port USB Specification, revision 2.0-
compatible host controller, based on the
OHCI Specification for USB, release 1.0
USB device compatible with the USB
Specification, revision 2.0 and USB
Specification, revision 1.1
•
– Consistent memory map across family
– Real-Time Interrupt Timer (RTI) OS Timer
– 128-channel Vectored Interrupt Module (VIM)
– 2-channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity protection for control packet RAM
– DMA Accesses Protected by Dedicated MPU
– Three CAN Controllers (DCAN)
•
•
64 mailboxes with parity protection each
Compliant to CAN protocol version
2.0A/B
– Inter-Integrated Circuit (I2C)
– Three Multi-buffered Serial Peripheral
Interfaces (MibSPI)
•
•
128 Words with Parity Protection each
8 Transfer groups
• Frequency-Modulated Phase-Locked-Loop
(FMPLL) with Built-In Slip Detector
• Separate Non-Modulating PLL
– Up to two Standard Serial Peripheral
Interfaces (SPI)
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight Components
• Advanced JTAG Security Module (AJSM)
• Trace and Calibration Capabilities
– Two UART (SCI) interfaces, one with Local
Interconnect Network Interface (LIN 2.1)
Support
• Up to 101 general purpose I/O (GIO) capable
pins
– Parameter Overlay Module (POM)
– 16 dedicated GIO pins with interrupt
generation capability
• Packages
• Enhanced Timing Peripherals for Motor Control
– 7 Enhanced Pulse Width Modulators (ePWM)
– 6 Enhanced Capture (eCAP)
– 144-pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
– 2 Enhanced Quadrature Encoder Pulse
(eQEP)
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas
Instruments reserves the right to change or discontinue these products without notice.
Copyright © 2012, Texas Instruments Incorporated
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