ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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SPI TIMING CHARACTERISTICS
tSPWH
tSCLK
tCSH
CS
tCSSC
tSPWL
SCLK
tDIST
DIN
B7
B7
B6
B5
B5
B4
tDOPD
B3
B3
B2
B2
B1
B1
B0
B0
tDIHD
DOUT
B6
B4
tCSDOD
tDOHD
tCSDOZ
Figure 1. Serial Interface Timing
TIMING REQUIREMENTS: SERIAL INTERFACE TIMING
At TA = –40°C to +105°C and DVDD = 2.7V to 5.25V, unless otherwise noted.
SYMBOL
tCSSC
DESCRIPTION
MIN
50
MAX
UNIT
CS low to first SCLK: setup time(1)
SCLK period
ns
(2)
tSCLK
1.8
90
tCLK
ns
tSPWH
SCLK pulse width: high
90
ns
tCLK
ns
tSPWL
SCLK pulse width: low(3)
216
60
tDIST
tDIHD
Valid DIN to SCLK falling edge: setup time
Valid DIN to SCLK falling edge: hold time
SCLK rising edge to valid new DOUT: propagation delay(4)
SCLK rising edge to DOUT invalid: hold time
CS low to DOUT driven: propagation delay(4)
CS high to DOUT Hi-Z: propagation delay
CS high pulse
35
20
ns
tDOPD
tDOHD
tCSDOD
tCSDOZ
tCSH
ns
0
0
ns
40
20
ns
ns
20
tCLK
(1) CS can be tied low.
(2) tCLK = 1/fCLK
.
(3) Holding SCLK low longer than 216 × tCLK cycles resets the SPI interface (enabled by SPI register bit).
(4) DOUT load = 20pF || 100kΩ to DGND.
6
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