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SLES081A − JUNE 2003 – REVISED MAY 2004
BLOCK DIAGRAM (PCM2704DB/PCM2705DB)
V
CCP
V
CCL
V
CCR
V
DD
PGND
AGNDL AGNDR DGND
ZGND
Power
Manager
SSPND
5-V to 3.3-V
Voltage Regulator
V
BUS
V
COM
USB
Protocol
Controller
Analog
PLL
V
OUT
L
DAC
D+
D–
Control
Endpoint
V R
OUT
S/PDIF Encoder
DOUT
EEPROM
Interface
CK
DT
†
ISO-Out
Endpoint
FIFO
HOST
HID0/MS
HID1/MC
HID2/MD
HID
Endpoint
SPI
Interface
PSEL
‡
TEST0
TEST1
96 MHz
Tracker
(SpAct)
PLL (×8)
XTI 12 MHz XTO
†
‡
Applies to PCM2704DB
Applies to PCM2705DB
8