PCM1794A
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
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t(SCKH)
H
2 V
System Clock (SCK)
0.8 V
L
t(SCKL)
t(SCY)
Figure 1. System Clock Input Timing
RST (Pin 14)
50 % of V
DD
t
(RST)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 2. External Reset Timing
50% of V
50% of V
50% of V
LRCK
BCK
DD
DD
DD
t
t
(BCL)
t
(BCH)
(LB)
t
t
t
(BCY)
(BL)
DATA
t
(DS)
(DH)
Figure 3. Timing of Audio Interface
8
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