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PCM1794ADBR 参数 Datasheet PDF下载

PCM1794ADBR图片预览
型号: PCM1794ADBR
PDF下载: 下载PDF文件 查看货源
内容描述: [132dB SNR 最高性能立体声 DAC(硬件控制) | DB | 28 | -25 to 85]
分类和应用: 光电二极管转换器
文件页数/大小: 37 页 / 900 K
品牌: TI [ TEXAS INSTRUMENTS ]
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PCM1794A  
ZHCSEE9B AUGUST 2004REVISED DECEMBER 2015  
www.ti.com.cn  
7.3.3 Audio Data Interface  
7.3.3.1 Audio Serial Interface  
The audio interface port is a 3-wire serial port that includes LRCK (pin 4), BCK (pin 6), and DATA (pin 5). BCK is  
the serial audio bit clock, and used to clock the serial data present on DATA into the serial shift register of the  
audio interface. Serial data is clocked into the PCM1794A device on the rising edge of BCK. LRCK is the serial  
audio left/right word clock.  
The PCM1794A device requires the synchronization of LRCK and the system clock, but does not require a  
specific phase relation between LRCK and the system clock.  
If the relationship between LRCK and the system clock changes more than ±6 BCK, internal operation is  
initialized within 1/fS, and the analog outputs are forced to the bipolar zero level until resynchronization between  
LRCK and the system clock is completed.  
7.3.3.2 PCM Audio Data Formats and Timing  
The PCM1794A device supports industry-standard audio data formats, including standard right-justified, I2S, and  
left-justified. The data formats are shown in Figure 22. Data formats are selected using the format bits, FMT1  
(pin 12), and FMT0 (pin 11) as shown in Table 3. All formats require binary twos-complement, MSB-first audio  
data. The Timing Requirements table lists and Figure 3 shows a detailed timing diagram for the serial audio  
interface.  
14  
Copyright © 2004–2015, Texas Instruments Incorporated  
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