PCM1794A
www.ti.com.cn
ZHCSEE9B –AUGUST 2004–REVISED DECEMBER 2015
7.3 Feature Description
7.3.1 System Clock Input
The PCM1794A device requires a system clock for operating the digital interpolation filters and advanced
segment DAC modulators. The system clock is applied at the SCK input (pin 7). The PCM1794A device has a
system clock detection circuit that automatically senses the frequency at which the system clock is operating.
Table 2 shows examples of system clock frequencies for common audio-sampling rates.
The Timing Requirements table lists and Figure 1 shows the timing requirements for the system clock input. For
optimal performance, use a clock source with low-phase jitter and noise. One of the Texas Instruments PLL1700
family of multiclock generators is an excellent selection for providing the PCM1794A system clock.
Table 2. System Clock Rates for Common Audio Sampling Frequencies
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
SAMPLING
FREQUENCY
128 fS
4.096
192 fS
6.144
256 fS
8.192
384 fS
12.288
16.9344
18.432
36.864
73.728
512 fS
16.384
22.5792
24.576
49.152
768 fS
24.576
33.8688
36.864
73.728
32 kHz
44.1 kHz
48 kHz
5.6488
6.144
8.4672
9.216
11.2896
12.288
24.576
49.152
96 kHz
12.288
24.576
18.432
36.864
(1)
(1)
192 kHz
See
See
(1) This system clock rate is not supported for the given sampling frequency.
7.3.2 Power-On and External Reset Functions
The PCM1794A device includes a power-on reset function. Figure 21 shows the operation of this function. With
VDD > 2 V, the power-on reset function is enabled. The initialization sequence requires 1024 system clocks from
the time VDD > 2 V.
The PCM1794A device also includes an external reset capability using the RST input (pin 14), which allows an
external controller or master reset circuit to force the PCM1794A device to initialize to its default reset state.
The Timing Requirements table lists and Figure 2 shows the external reset operation and timing. The RST pin is
set to logic 0 for a minimum of 20 ns. The RST pin is then set to a logic 1 state to start the initialization
sequence, which requires 1024 system clock periods. The external reset is useful in applications with a delay
between the PCM1794A power-up and system clock activation.
V
DD
2.4 V (Max)
2 V (Typ)
1.6 V (Min)
Reset
Reset Removal
Internal Reset
System Clock
1024 System Clocks
Figure 21. Power-On Reset Timing
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