The PCI6x21/PCI6x11 controller is a serial bus master; all other devices connected to the serial bus external to the
PCI6x21/PCI6x11 controller are slave devices. As the bus master, the PCI6x21/PCI6x11 controller drives the SCL
clock at nearly 100 kHz during bus cycles and places SCL in a high-impedance state (zero frequency) during idle
states.
Typically, the PCI6x21/PCI6x11 controller masters byte reads and byte writes under software control. Doubleword
reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under
software control. See Section 3.6.4, Serial-Bus EEPROM Application, for details on how the PCI6x21/PCI6x11
controller automatically loads the subsystem identification and other register defaults through a serial-bus EEPROM.
Figure 3−8 illustrates a byte write. The PCI6x21/PCI6x11 controller issues a start condition and sends the 7-bit slave
device address and the command bit zero. A 0 in the R/W command bit indicates that the data transfer is a write. The
slave device acknowledges if it recognizes the address. If no acknowledgment is received by the PCI6x21/PCI6x11
controller, then an appropriate status bit is set in the serial-bus control/status register (PCI offset B3h, see
Section 4.50). The word address byte is then sent by the PCI6x21/PCI6x11 controller, and another slave
acknowledgment is expected. Then the PCI6x21/PCI6x11 controller delivers the data byte MSB first and expects a
final acknowledgment before issuing the stop condition.
Slave Address
Word Address
Data Byte
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
P
R/W
A = Slave Acknowledgement
S/P = Start/Stop Condition
Figure 3−8. Serial-Bus Protocol—Byte Write
Figure 3−9 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W command
bit must be set to 1 to indicate a read-data transfer. In addition, the PCI6x21/PCI6x11 master must acknowledge
reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA signal during read data
transfers. The SCL signal remains driven by the PCI6x21/PCI6x11 master.
Slave Address
Word Address
Slave Address
S
b6 b5 b4 b3 b2 b1 b0
0
A
b7 b6 b5 b4 b3 b2 b1 b0
A
S
b6 b5 b4 b3 b2 b1 b0
1
A
Start
R/W
Restart
R/W
Data Byte
b7 b6 b5 b4 b3 b2 b1 b0
M
P
Stop
A = Slave Acknowledgement
M = Master Acknowledgement
S/P = Start/Stop Condition
Figure 3−9. Serial-Bus Protocol—Byte Read
Figure 3−10 illustrates EEPROM interface doubleword data collection protocol.
3−11
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