Table 3−6. CardBus Socket Registers
REGISTER NAME
OFFSET
Socket event
Socket mask
00h
04h
Socket present state
Socket force event
Socket control
08h
0Ch
10h
Reserved
14h−1Ch
20h
Socket power management
3.5.11 48-MHz Clock Requirements
The PCI6x21/PCI6x11 controller is designed to use an external 48-MHz clock connected to the CLK_48 terminal to
provide the reference for an internal oscillator circuit. This oscillator in turn drives a PLL circuit that generates the
various clocks required for the flash media function (Function 3) of the PCI6x21/PCI6x11 controller.
The 48-MHz clock must maintain a frequency of 48 MHz 0.8% over normal operating conditions. This clock must
maintain a duty cycle of 40% − 60%. The PCI6x21/PCI6x11 controller requires that the 48-MHz clock be running and
stable (a minimum of 10 clock pulses) before a GRST deassertion.
The following are typical specifications for crystals used with the PCI6x21/PCI6x11 controller in order to achieve the
required frequency accuracy and stability.
•
•
Crystal mode of operation: Fundamental
Frequency tolerance @ 25°C: Total frequency variation for the complete circuit is 100 ppm. A crystal with
30 ppm frequency tolerance is recommended for adequate margin.
•
Frequency stability (over temperature and age): A crystal with 30 ppm frequency stability is recommended
for adequate margin.
NOTE: The total frequency variation must be kept below 100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between frequency
tolerance and stability may be made as long as the total frequency variation is less than
100 ppm. For example, the frequency tolerance of the crystal may be specified at 50 ppm and
the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible
variation due to the crystal alone. Crystal aging also contributes to the frequency variation.
3.6 Serial EEPROM Interface
The PCI6x21/PCI6x11 controller has a dedicated serial bus interface that can be used with an EEPROM to load
certain registers in the PCI6x21/PCI6x11 controller. The EEPROM is detected by a pullup resistor on the SCL
terminal. See Table 3−8 for the EEPROM loading map.
3.6.1 Serial-Bus Interface Implementation
The PCI6x21/PCI6x11 controller drives SCL at nearly 100 kHz during data transfers, which is the maximum specified
2
frequency for standard mode I C. The serial EEPROM must be located at address A0h.
Some serial device applications may include PC Card power switches, card ejectors, or other devices that may
enhance the user’s PC Card experience. The serial EEPROM device and PC Card power switches are discussed
in the sections that follow.
3.6.2 Accessing Serial-Bus Devices Through Software
The PCI6x21/PCI6x11 controller provides a programming mechanism to control serial bus devices through software.
The programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−7 lists
the registers used to program a serial-bus device through software.
3−9
TI [ TEXAS INSTRUMENTS ]
