Table 2−14. CardBus PC Card Interface Control Terminals
If any CardBus PC Card interface control terminal is unused, then the terminal may be left floating.
†
SKT A TERMINAL
SKT B TERMINAL
I/O
TYPE
PU/
PD
POWER
RAIL
DESCRIPTION
INPUT OUTPUT
NAME
NO.
NAME
NO.
CardBus audio. CAUDIO is a digital input signal from
a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary
signal from the card to SPKROUT.
V
V
/
CCA
CCB
A_CAUDIO
A02
E10
B_CAUDIO
C17
I
PCII4
PCII4
PCIO4
PCIO4
PU3
PU3
V
V
/
CardBus lock. CBLOCK is used to gain exclusive
access to a target.
CCA
CCB
J19
I/O
A_CBLOCK
B_CBLOCK
CardBus detect 1 and CardBus detect 2. CCD1 and
CCD2 are used in conjunction with CVS1 and CVS2
to identify card insertion and interrogate cards to
determine the operating voltage and card type.
C15
E05
N13
B17
A_CCD1
A_CCD2
B_CCD1
B_CCD2
I
TTLI2
PCII4
PU4
PU3
CardBus device select. The controller asserts
CDEVSEL to claim a CardBus cycle as the target
device. As a CardBus initiator on the bus, the
controller monitors CDEVSEL until a target responds.
If no target responds before timeout occurs, then the
controller terminates the cycle with an initiator abort.
V
V
/
/
CCA
CCB
C09
C08
H19
G19
I/O
PCIO4
PCIO7
A_CDEVSEL
A_CFRAME
B_CDEVSEL
B_CFRAME
CardBus cycle frame. CFRAME is driven by the
initiator of a CardBus bus cycle. CFRAME is asserted
to indicate that a bus transaction is beginning, and
data transfers continue while this signal is asserted.
When CFRAME is deasserted, the CardBus bus
transaction is in the final data phase.
V
V
CCA
CCB
I/O
PCII7
CardBus bus grant. CGNT is driven by the controller
to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been
completed.
V
V
/
/
CCA
CCB
B09
C04
J15
O
I
PCII7
PCII4
PCIO7
PCIO4
A_CGNT
A_CINT
B_CGNT
B_CINT
V
V
CardBus interrupt. CINT is asserted low by a CardBus
PC Card to request interrupt servicing from the host.
CCA
CCB
B19
PU3
PU3
CardBus initiator ready. CIRDY indicates the ability of
the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed
on a rising edge of CCLK when both CIRDY and
CTRDY are asserted. Until CIRDY and CTRDY are
both sampled asserted, wait states are inserted.
V
V
/
CCA
CCB
B08
J13
I/O
PCII4
PCIO4
A_CIRDY
B_CIRDY
CardBus parity error. CPERR reports parity errors
during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following
the data cycle during which a parity error is detected.
V
V
/
/
CCA
CCB
F10
E07
J18
I/O
I
PCII4
PCII4
PCIO4
PCIO4
PU3
PU3
A_CPERR
A_CREQ
B_CPERR
B_CREQ
CardBus request. CREQ indicates to the arbiter that
the CardBus PC Card desires use of the CardBus bus
as an initiator.
V
V
CCA
CCB
E18
CardBus system error. CSERR reports address parity
errors and other system errors that could lead to
catastrophic results. CSERR is driven by the card
synchronous to CCLK, but deasserted by a weak
pullup; deassertion may take several CCLK periods.
The controller can report CSERR to the system by
assertion of SERR on the PCI interface.
V
V
/
CCA
CCB
B03
B18
I
PCII4
PCIO4
PU3
A_CSERR
B_CSERR
†
These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−24
TI [ TEXAS INSTRUMENTS ]
