Table 2−12. CardBus PC Card Interface System Terminals
A 33-Ω to 47-Ω series damping resistor (per PC Card specification) is the only external component needed for
terminals B08 (A_CCLK) and H17 (B_CCLK). If any CardBus PC Card interface system terminal is unused, then the
terminal may be left floating.
†
SKT A TERMINAL
SKT B TERMINAL
I/O
TYPE
PU/
PD
POWER
RAIL
DESCRIPTION
INPUT OUTPUT
NAME NO.
NAME
NO.
CardBus clock. CCLK provides synchronous timing
for all transactions on the CardBus interface. All
signals except CRST, CCLKRUN, CINT, CSTSCHG,
CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
sampled on the rising edge of CCLK, and all timing
parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock
frequency, but it can be stopped in the low state or
slowed down for power savings.
V
V
/
CCA
CCB
A_CCLK
E09
B_CCLK
H18
O
PCIO3
CardBus clock run. CCLKRUN is used by a CardBus
PC Card to request an increase in the CCLK
frequency, and by the controller to indicate that the
CCLK frequency is going to be decreased.
V
V
/
CCA
CCB
C03
A06
A18
F17
I/O
O
PCII4
PCII4
PCIO4
PCIO4
PU3
PU3
A_CCLKRUN
A_CRST
B_CCLKRUN
B_CRST
CardBus reset. CRST brings CardBus PC
Card-specific registers, sequencers, and signals to a
known state. When CRST is asserted, all CardBus
PC Card signals are placed in a high-impedance
state, and the controller drives these signals to a valid
logic level. Assertion can be asynchronous to CCLK,
but deassertion must be synchronous to CCLK.
V
V
/
CCA
CCB
†
These terminals are reserved for the PCI6611 and PCI6411 controllers.
2−22
TI [ TEXAS INSTRUMENTS ]
