欢迎访问ic37.com |
会员登录 免费注册
发布采购

PCI6421 参数 Datasheet PDF下载

PCI6421图片预览
型号: PCI6421
PDF下载: 下载PDF文件 查看货源
内容描述: 双/单插槽的CardBus和UltraMedia控制器 [DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER]
分类和应用: 控制器
文件页数/大小: 204 页 / 849 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号PCI6421的Datasheet PDF文件第111页浏览型号PCI6421的Datasheet PDF文件第112页浏览型号PCI6421的Datasheet PDF文件第113页浏览型号PCI6421的Datasheet PDF文件第114页浏览型号PCI6421的Datasheet PDF文件第116页浏览型号PCI6421的Datasheet PDF文件第117页浏览型号PCI6421的Datasheet PDF文件第118页浏览型号PCI6421的Datasheet PDF文件第119页  
Table 5−1. ExCA Registers and Offsets  
PCI MEMORY ADDRESS EXCA OFFSET EXCA OFFSET  
EXCA REGISTER NAME  
OFFSET (HEX)  
(CARD A)  
(CARD B)  
Identification and revision ‡  
800  
00  
40  
Interface status  
801  
01  
41  
Power control †  
802†  
803†  
804†  
805†  
806  
02  
42  
Interrupt and general control †  
03  
43  
Card status change †  
04  
44  
Card status change interrupt configuration †  
Address window enable  
05  
45  
06  
46  
I / O window control  
807  
07  
47  
I / O window 0 start-address low-byte  
I / O window 0 start-address high-byte  
I / O window 0 end-address low-byte  
I / O window 0 end-address high-byte  
I / O window 1 start-address low-byte  
I / O window 1 start-address high-byte  
I / O window 1 end-address low-byte  
I / O window 1 end-address high-byte  
Memory window 0 start-address low-byte  
Memory window 0 start-address high-byte  
Memory window 0 end-address low-byte  
Memory window 0 end-address high-byte  
Memory window 0 offset-address low-byte  
Memory window 0 offset-address high-byte  
Card detect and general control †  
Reserved  
808  
08  
48  
809  
09  
49  
80A  
80B  
80C  
80D  
80E  
80F  
0A  
0B  
0C  
0D  
0E  
0F  
10  
4A  
4B  
4C  
4D  
4E  
4F  
50  
810  
811  
11  
51  
812  
12  
52  
813  
13  
53  
814  
14  
54  
815  
15  
55  
816  
16  
56  
817  
17  
57  
Memory window 1 start-address low-byte  
Memory window 1 start-address high-byte  
Memory window 1 end-address low-byte  
Memory window 1 end-address high-byte  
Memory window 1 offset-address low-byte  
Memory window 1 offset-address high-byte  
Global control ‡  
818  
18  
58  
819  
19  
59  
81A  
81B  
81C  
81D  
81E  
81F  
1A  
1B  
1C  
1D  
1E  
1F  
20  
5A  
5B  
5C  
5D  
5E  
5F  
60  
Reserved  
Memory window 2 start-address low-byte  
Memory window 2 start-address high-byte  
Memory window 2 end-address low-byte  
Memory window 2 end-address high-byte  
Memory window 2 offset-address low-byte  
Memory window 2 offset-address high-byte  
820  
821  
21  
61  
822  
22  
62  
823  
23  
63  
824  
24  
64  
825  
25  
65  
One or more bits in this register are cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared  
by the assertion of PRST or GRST.  
One or more bits in this register are cleared only by the assertion of GRST.  
5−3  
 复制成功!