Digital Interface
All of the pins on J4 and J8 are connected with minimal filtering or protection. Use appropriate caution
when handling these pins.
summarizes the pinouts for analog interfaces J4 and J8.
Table 1. J8/J4: Analog Interface Pinout
Pin Number
J8.1, J4-1
J8.2, J4-2
J8.3, J4-3
J8.4, J4-4
J8.5, J4-5
J8.6, J4-6
J8.7, J4-7
J8.8, J4-8
J8.18
J8.20
J8.10-16 (even)
J8.15
J8.9-19 (odd), J4-9
Signal
A0(–)
A0(+)
A1(–)
A1(+)
A2(–)
A2(+)
A3(–)
A3(+)
REF–
REF+
Unused
Unused
AGND
Analog ground connections
(except J8.15)
Description, ADS1148/ADS1248
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
External reference source input (–
side of differential input)
External reference source input (+
side of differential input)
3
3.1
Digital Interface
Serial Data Interface
The ADS1248EVM is designed to easily interface with multiple control platforms. Samtec part numbers
SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin, dual-row, header/socket
combination at J7. This header/socket provides access to the digital control and serial data pins of the
ADC. Consult Samtec at
or call 1-800-SAMTEC-9 for a variety of mating
connector options.
All logic levels on J7 are 3.3V CMOS, except for the I
2
C™ pins. These pins conform to 3.3V I
2
C rules.
describes the J7 serial interface pins.
Table 2. J7: Serial Interface Pins
Pin No.
J7.1
J7.2
J7.3
J7.4
J7.5
J7.6
J7.7
J7.8
J7.9
J7.10
J7.11
J7.12
J7.13
J7.14
J7.15
Pin Name
CNTL
GPIO0
CLKX
DGND
CLKR
GPIO1
FSX
GPIO2
FSR
DGND
DX
GPIO3
DR
GPIO4
INT
Signal Name
CS
START
SCLK
DGND
Unused
MR
Unused
Unused
DRDY
DGND
DIN
PWRSEL
DOUT/DRDY
Unused
DRDY
I/O Type
In
In
In
In/Out
–
In
–
–
Out
In/Out
In
In
Out
–
Out
Pullup
High
High
None
None
–
High
–
–
None
None
None
High
None
–
None
Digital ground
ADS1248 SPI data in
Selects
±2.5V
or +5V
supply
ADS1248 data out
Master reset
ADS1248 SPI clock
Digital ground
Function
4
ADS1148EVM, ADS1248EVM, ADS1148EVM-PDK, and ADS1248EVM-PDK
Copyright
©
2009–2011, Texas Instruments Incorporated
SBAU142B
–
April 2009
–
Revised May 2011