XIO3130
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BIT
SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-83. Bit Descriptions – General Control Register (continued)
FIELD NAME
ACCESS
DESCRIPTION
PCI Hot Plug surprise. This bit indicates whether a device present in this slot can be removed
from the system without prior notification. This bit is used to control the PCI Hot Plug surprise
(HPS) field in the Slot Capabilities register.
0 – No device present that can be removed without prior notification
1 – Device present that can be removed without prior notification.
13
SLOT_HPS
rw
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
Power indicator present. This bit indicates whether a power indicator is implemented on the
chassis for this slot. This bit is used to control the PIP field in the Slot Capabilities register.
0 – Power indicator not implemented
12
11
SLOT_PIP
SLOT_AIP
rw
rw
1 – Power indicator implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Attention indicator present. This bit indicates whether an attention indicator is implemented on
the chassis for this slot. This bit is used to control the AIP field in the Slot Capabilities register.
0 – Attention indicator not implemented
1 – Attention indicator implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Manual retention latch sensor present. This bit indicates whether an MRL sensor is
implemented on the chassis for this slot. This bit is used to control the MRLSP field in the Slot
Capabilities register.
10
SLOT_MRLSP
SLOT_PCP
SLOT_ABP
rw
rw
rw
0 – MRL sensor not implemented
1 – MRL sensor implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Power controller present. This bit indicates whether a power controller is implemented for this
slot to control power. This bit is used to control the power controller present (PCP) field in the
Slot Capabilities register.
9
0 – Power controller not implemented
1 – Power controller implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Attention button present. This bit indicates whether an attention button is implemented on the
chassis for this slot. This bit is used to control the attention button present (ABP) field in the Slot
Capabilities register.
8
0 – Attention button not implemented
1 – Attention button implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Slot implemented. This bit indicates that the downstream port is connected to an add-in card
slot (e.g., PCI Express, ExpressCard, etc.). This bit is used to control the SLOT bit in the PCI
Express Capabilities register.
0 – Port not connected to slot
1 – Port connected to slot
7
6
SLOT_PRSNT
rw
rw
This field is loaded from EEPROM (if present) and reset with PERST. The default value for this
bit is that of the DNn_DPSTRP pin for the associated port.
Power fault input present. This bit indicates whether an input pin is used as a power fault
detection input for this slot. This bit is used to control whether the power fault input pin is used,
e.g., for disabling the REFCLK output buffer.
SLOT_PFIP
0 – Power fault input not implemented
1 – Power fault input implemented
This field is loaded from EEPROM (if present) and reset with PERST.
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
119
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