ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢄ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇ ꢃ ꢆ ꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇꢃ ꢆꢇ
ꢀ ꢉꢊꢋ ꢌ ꢁꢉ ꢍ ꢎꢏꢐ ꢀ ꢉꢑꢒꢓ ꢑꢓ ꢎꢔ ꢒꢓ ꢐꢐ ꢋꢒ
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
= −1 mA,
= −6 mA,
= −1 mA,
= −6 mA,
= 1.5 mA,
= 6 mA,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V,
= 2.2 V,
= 3 V,
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
OH(max)
OH(max)
OH(max)
OH(max)
OL(max)
OL(max)
OL(max)
OL(max)
CC
CC
CC
CC
CC
V
−0.6
CC
−0.25
V
High-level output voltage
V
OH
OL
V
CC
= 3 V,
V
−0.6
CC
= 2.2 V,
= 2.2 V,
= 3 V,
V
V
+0.25
SS
SS
SS
SS
SS
V
V
V
V
+0.6
SS
V
Low-level output voltage
V
= 1.5 mA,
= 6 mA,
V
SS
+0.25
= 3 V,
V
+0.6
SS
NOTES: 1. The maximum total current, I
specified voltage drop.
and I
for all outputs combined, should not exceed 6 mA to satisfy the maximum
OH(max)
OL(max),
and I
OL(max),
2. The maximum total current, I
specified voltage drop.
for all outputs combined, should not exceed 24 mA to satisfy the maximum
OH(max)
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA0..2, TB0−TB6,
f
Internal clock source, SMCLK signal
applied (see Note 1)
C
C
= 20 pF
= 20 pF
DC
f
f
TAx
L
L
System
MHz
f
f
f
ACLK,
MCLK,
SMCLK
P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK
System
f
f
f
f
f
= f
= f
40%
30%
60%
70%
ACLK LFXT1 XT1
P2.0/ACLK
= f
= f
C
= 20 pF,
= 2.2 V / 3 V
ACLK LFXT1 LF
L
V
CC
= f
50%
ACLK LFXT1/n
= f
= f
SMCLK LFXT1 XT1
40%
35%
60%
65%
t
Duty cycle of output frequency,
Xdc
= f
= f
SMCLK LFXT1 LF
P1.4/SMCLK,
50%−
15 ns
50%−
15 ns
C
= 20 pF,
= 2.2 V / 3 V
f
= f
50%
50%
L
SMCLK LFXT1/n
V
CC
50%−
15 ns
50%−
15 ns
f = f
SMCLK DCOCLK
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK
frequencies can be different.
27
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TI [ TEXAS INSTRUMENTS ]
