MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
Internal: SMCLK, ACLK
External: UCLK
f
USCI input clock frequency
f
MHz
USCI
SYSTEM
Duty cycle = 50% 10%
Maximum BITCLK clock frequency
(equals baudrate in MBaud)
(see Note 1)
fmax,
2.2V /3 V
2
MHz
ns
BITCLK
2.2 V
3 V
50
50
150
100
UART receive deglitch time
(see Note 2)
t
NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.
2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.
USCI (SPI master mode) (see Figure 19 and Figure 20)
PARAMETER
TEST CONDITIONS
V
MIN
MAX UNIT
CC
SMCLK, ACLK
Duty cycle = 50% 10%
f
t
t
t
USCI input clock frequency
f
MHz
ns
USCI
SYSTEM
2.2 V
3 V
110
75
0
SOMI input data setup time
SOMI input data hold time
SU,MI
2.2 V
3 V
ns
HD,MI
0
2.2 V
3 V
30
20
UCLK edge to SIMO valid,
SIMO output data valid time
ns
VALID,MO
C
L
= 20 pF
1
NOTE: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
2tLO∕HI
For the slave’s parameters t
and t
refer to the SPI parameters of the attached slave.
VALID,SO(Slave)
SU,SI(Slave)
USCI (SPI slave mode) (see Figure 21 and Figure 22)
PARAMETER
TEST CONDITIONS
V
MIN
TYP
MAX UNIT
CC
STE lead time
STE low to clock
t
t
t
t
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
2.2 V/3 V
50
ns
STE,LEAD
STE,LAG
STE,ACC
STE,DIS
STE lag time
Last clock to STE high
10
ns
ns
ns
STE access time
STE low to SOMI data out
50
50
STE disable time
STE high to SOMI high impedance
2.2 V
3 V
20
15
10
10
t
t
t
SIMO input data setup time
SIMO input data hold time
ns
SU,SI
2.2 V
3 V
ns
HD,SI
2.2 V
3 V
75
50
110
UCLK edge to SOMI valid,
= 20 pF
SOMI output data valid time
ns
75
VALID,SO
C
L
1
NOTE: fUCxCLK
=
with tLO∕HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).
2tLO∕HI
For the master’s parameters t
and t
refer to the SPI parameters of the attached master.
VALID,MO(Master)
SU,MI(Master)
45
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