MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
TEST
CONDITIONS
PARAMETER
V
MIN NOM
MAX
UNIT
CC
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.2
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from DV during program
2.5V/3.6V
2.5V/3.6V
2.5V/3.6V
2.5V/3.6V
3
PGM
CC
Supply current from DV during erase
CC
3
7
mA
ERASE
CPT
Cumulative program time
Cumulative mass erase time
Program/Erase endurance
Data retention duration
see Note 1
see Note 2
10
ms
200
ms
CMErase
4
5
10
100
10
cycles
years
t
T = 25C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writingto a64--byte flashblock. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297x1 / f , max = 5297 x 1 / 476 kHz).
FTG
To achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is
met. (A worst case minimum of 19 cycles is required.)
3. These values are hardwired into the Flash Controller’s state machine (t
= 1 / f
).
FTG
FTG
JTAG and Spy-Bi-Wire interface
TEST
CONDITIONS
PARAMETER
V
MIN
TYP
MAX
UNIT
CC
f
t
Spy-Bi-Wire input frequency
2.2 V/3 V
2.2 V/3 V
0
8
MHz
us
SBW
Spy-Bi-Wire low clock pulse length
0.025
15
SBW,Low
Spy-Bi-Wire enable time,
TEST high to acceptance of first clock edge
(see Note 1)
t
2.2 V/3 V
1
us
SBW,En
t
f
Spy-Bi-Wire return to normal operation time
2.2 V/3 V
2.2 V
15
0
100
5
us
SBW,Ret
TCK
MHz
MHz
k
TCK input frequency (see Note 2)
3 V
0
10
90
R
Internal pulldown resistance on TEST
2.2 V/3 V
25
60
Internal
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum t
before applying the first SBWCLK clock edge.
time after pulling the TEST/SBWCLK pin high
SBW,En
2.
f
may be restricted to meet the timing requirements of the module selected.
TCK
49
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