MSP430G2x53
MSP430G2x13
www.ti.com
SLAS735A –APRIL 2011–REVISED MAY 2011
USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and
Figure 19)
PARAMETER
TEST CONDITIONS
VCC
3 V
3 V
3 V
MIN
TYP
MAX UNIT
tSTE,LEAD
tSTE,LAG
tSTE,ACC
STE lead time, STE low to clock
STE lag time, Last clock to STE high
STE access time, STE low to SOMI data out
50
ns
ns
ns
10
50
50
STE disable time, STE high to SOMI high
impedance
tSTE,DIS
3 V
ns
tSU,SI
tHD,SI
SIMO input data setup time
SIMO input data hold time
3 V
3 V
15
10
ns
ns
UCLK edge to SOMI valid,
CL = 20 pF
tVALID,SO
SOMI output data valid time
3 V
50
75
ns
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 18. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 19. SPI Slave Mode, CKPH = 1
Copyright © 2011, Texas Instruments Incorporated
Submit Documentation Feedback
33
TI [ TEXAS INSTRUMENTS ]
