MSP430G2x53
MSP430G2x13
SLAS735A –APRIL 2011–REVISED MAY 2011
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USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
SMCLK, duty cycle = 50% ± 10%
fSYSTEM
MHz
Maximum BITCLK clock frequency
(equals baudrate in MBaud)(1)
UART receive deglitch time(2)
fmax,BITCLK
tτ
3 V
3 V
2
MHz
50
100
600
ns
(1) The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.
(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and
Figure 17)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fUSCI
USCI input clock frequency
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
SMCLK, duty cycle = 50% ± 10%
fSYSTEM MHz
tSU,MI
3 V
3 V
3 V
75
0
ns
ns
tHD,MI
tVALID,MO
UCLK edge to SIMO valid, CL = 20 pF
20
ns
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 16. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 17. SPI Master Mode, CKPH = 1
32
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