MSP430FR573x
MSP430FR572x
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SLAS639D –JULY 2011–REVISED AUGUST 2012
eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
UCSTEM = 0,
UCMODEx = 01 or 10
2 V, 3 V
1
UCxCLK
cycles
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
STE lead time, STE active to clock
UCSTEM = 1,
UCMODEx = 01 or 10
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
1
1
1
UCSTEM = 0,
UCMODEx = 01 or 10
STE lag time, Last clock to STE
inactive
UCxCLK
cycles
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
55
35
40
30
STE access time, STE active to SIMO
data out
ns
ns
UCSTEM = 1,
UCMODEx = 01 or 10
UCSTEM = 0,
UCMODEx = 01 or 10
STE disable time, STE inactive to
SIMO high impedance
UCSTEM = 1,
UCMODEx = 01 or 10
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
35
35
0
tSU,MI
SOMI input data setup time
SOMI input data hold time
ns
ns
ns
ns
tHD,MI
0
30
30
UCLK edge to SIMO valid,
CL = 20 pF
(2)
tVALID,MO
SIMO output data valid time
0
0
(3)
tHD,MO
SIMO output data hold time
CL = 20 pF
(1) fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 6 and Figure 7.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 6
and Figure 7.
Copyright © 2011–2012, Texas Instruments Incorporated
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