MSP430FR573x
MSP430FR572x
SLAS639D –JULY 2011–REVISED AUGUST 2012
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Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
8
fTA
Timer_A input clock frequency
External: TACLK
Duty cycle = 50% ± 10%
2 V, 3 V
MHz
(1)
24
All capture inputs, Minimum pulse
duration required for capture
tTA,cap
Timer_A capture timing
2 V, 3 V
20
ns
(1) MSP430FR573x devices only
Timer_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
8
fTB
Timer_B input clock frequency
External: TBCLK
Duty cycle = 50% ± 10%
2 V, 3 V
MHz
(1)
24
All capture inputs, Minimum pulse
duration required for capture
tTB,cap
Timer_B capture timing
2 V, 3 V
20
ns
(1) MSP430FR573x devices only
eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
CONDITIONS
VCC
MIN
TYP
MAX UNIT
Internal: SMCLK, ACLK
External: UCLK
feUSCI
eUSCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ± 10%
BITCLK clock frequency
(equals baud rate in MBaud)
fBITCLK
5
MHz
eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
VCC
MIN
5
TYP
15
MAX UNIT
20
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
20
35
50
45
60
ns
(1)
tt
UART receive deglitch time
2 V, 3 V
80
120
110
180
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
58
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