MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Table 32. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
System control
SYSCTL
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
Bootstrap loader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
SYSRSTIV
Table 33. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
REFCTL
OFFSET
OFFSET
Shared reference control
00h
Table 34. Port Mapping Controller (Base Address: 01C0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
Port mapping password register
Port mapping control register
00h
02h
PMAPCTL
Table 35. Port Mapping for Port P1 (Base Address: 01C8h)
REGISTER DESCRIPTION
REGISTER
P1MAP0
OFFSET
Port P1.0 mapping register
Port P1.1 mapping register
Port P1.2 mapping register
Port P1.3 mapping register
Port P1.4 mapping register
Port P1.5 mapping register
Port P1.6 mapping register
Port P1.7 mapping register
00h
01h
02h
03h
04h
05h
06h
07h
P1MAP1
P1MAP2
P1MAP3
P1MAP4
P1MAP5
P1MAP6
P1MAP7
Table 36. Port Mapping for Port P2 (Base Address: 01D0h)
REGISTER DESCRIPTION
REGISTER
P2MAP0
OFFSET
Port P2.0 mapping register
Port P2.1 mapping register
Port P2.2 mapping register
Port P2.3 mapping register
Port P2.4 mapping register
Port P2.5 mapping register
Port P2.6 mapping register
Port P2.7 mapping register
00h
01h
02h
03h
04h
05h
06h
07h
P2MAP2
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
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