MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Table 6. Terminal Functions, MSP430F67xxIPN (continued)
TERMINAL
NAME
NO. I/O(1)
PN
DESCRIPTION
General-purpose digital I/O
LCD segment output S15
P5.0/S15
P5.1/S14
57
58
I/O
I/O
General-purpose digital I/O
LCD segment output S14
Digital power supply for I/Os
DVSYS(5)
DVSS
59
60
Digital ground supply
General-purpose digital I/O
LCD segment output S13
P5.2/S13
P5.3/S12
P5.4/S11
P5.5/S10
P5.6/S9
P5.7/S8
P6.0/S7
P6.1/S6
P6.2/S5
P6.3/S4
P6.4/S3
P6.5/S2
P6.6/S1
P6.7/S0
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General-purpose digital I/O
LCD segment output S12
General-purpose digital I/O
LCD segment output S11
General-purpose digital I/O
LCD segment output S10
General-purpose digital I/O
LCD segment output S9
General-purpose digital I/O
LCD segment output S8
General-purpose digital I/O
LCD segment output S7
General-purpose digital I/O
LCD segment output S6
General-purpose digital I/O
LCD segment output S5
General-purpose digital I/O
LCD segment output S4
General-purpose digital I/O
LCD segment output S3
General-purpose digital I/O
LCD segment output S2
General-purpose digital I/O
LCD segment output S1
General-purpose digital I/O
LCD segment output S0
Test mode pin – select digital I/O on JTAG pins
Spy-Bi-Wire input clock
TEST/SBWTCK
General-purpose digital I/O
SMCLK clock output
Test data output
PJ.0/SMCLK/TDO
76
77
I/O
I/O
General-purpose digital I/O
MCLK clock output
PJ.1/MCLK/TDI/TCLK
Test data input or Test clock input
(5) The pins VDSYS and DVSYS must be connected externally on board for proper device operation.
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