MSP430F673x
MSP430F672x
www.ti.com
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9. Interrupt Sources, Flags, and Vectors of MSP430F67xx Configurations
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-Up
External Reset
WDTIFG, KEYV (SYSRSTIV)(1)(2)
Reset
0FFFEh
0FFFCh
63, highest
Watchdog Timeout, Key Violation
Flash Memory Key Violation
System NMI
PMM
Vacant Memory Access
JTAG Mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
(Non)maskable
62
(1)(3)
JMBOUTIFG (SYSSNIV)
User NMI
NMI
Oscillator Fault
NMIIFG, OFIFG, ACCVIFG, AUXSWNMIFG
(SYSUNIV)(1)(3)
(Non)maskable
Maskable
0FFFAh
0FFF8h
61
60
Flash Memory Access Violation
Supply Switch
Watchdog Timer_A Interval Timer
Mode
WDTIFG
eUSCI_A0 Receive/Transmit
eUSCI_B0 Receive/Transmit
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1)(4)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1)(4)
Maskable
Maskable
0FFF6h
0FFF4h
59
58
ADC10IFG0, ADC10INIFG, ADC10LOIFG,
ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG
(ADC10IV)(1)(4)
ADC10_A
Maskable
0FFF2h
57
SD24_B
SD24_B Interrupt Flags (SD24IV)(1)(4)
TA0CCR0 CCIFG0(4)
Maskable
Maskable
0FFF0h
0FFEEh
56
55
Timer TA0
TA0CCR1 CCIFG1, TA0CCR2 CCIFG2,
TA0IFG (TA0IV)(1)(4)
Timer TA0
Maskable
0FFECh
54
eUSCI_A1 Receive/Transmit
eUSCI_A2 Receive/Transmit
Auxiliary Supplies
DMA
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1)(4)
UCA2RXIFG, UCA2TXIFG (UCA2IV)(1)(4)
Auxiliary Supplies Interrupt Flags (AUXIV)(1)(4)
DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1)(4)
TA1CCR0 CCIFG0(4)
Maskable
Maskable
Maskable
Maskable
Maskable
0FFEAh
0FFE8h
0FFE6h
0FFE4h
0FFE2h
53
52
51
50
49
Timer TA1
TA1CCR1 CCIFG1,
TA1IFG (TA1IV)(1)(4)
Timer TA1
Maskable
0FFE0h
48
I/O Port P1
Timer TA2
P1IFG.0 to P1IFG.7 (P1IV)(1)(4)
TA2CCR0 CCIFG0(4)
Maskable
Maskable
0FFDEh
0FFDCh
47
46
TA2CCR1 CCIFG1,
TA2IFG (TA2IV)(1)(4)
Timer TA2
Maskable
0FFDAh
45
I/O Port P2
Timer TA3
P2IFG.0 to P2IFG.7 (P2IV)(1)(4)
TA3CCR0 CCIFG0(4)
Maskable
Maskable
0FFD8h
0FFD6h
44
43
TA3CCR1 CCIFG1,
TA3IFG (TA3IV)(1)(4)
LCD_C Interrupt Flags (LCDCIV)(1)(4)
Timer TA3
LCD_C
Maskable
Maskable
Maskable
0FFD4h
0FFD2h
0FFD0h
42
41
40
RTCOFIFG, RTCRDYIFG, RTCTEVIFG,
RTC_C
RTCAIFG, RT0PSIFG, RT1PSIFG (RTCIV)(1)(4)
(1) Multiple source flags
(2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(3) (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
(4) Interrupt flags are located in the module.
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
21
TI [ TEXAS INSTRUMENTS ]
