MSP430F673x
MSP430F672x
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SLAS731A –DECEMBER 2011–REVISED APRIL 2012
Table 85. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS/ SIGNALS(1)
JTAG
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
PJSEL.x
Mode
Signal
PJ.0/SMCLK/TDO
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
0
PJ.0 (I/O)(2)
SMCLK
TDO(3)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
0
1
0
0
1
0
0
1
0
0
1
1
X
1
2
3
PJ.1 (I/O)(2)
I: 0; O: 1
MCLK
1
(3)(4)
TDI/TCLK
X
PJ.2 (I/O)(2)
I: 0; O: 1
ADC10CLK
1
(3)(4)
TMS
X
PJ.3 (I/O)(2)
I: 0; O: 1
ACLK
1
(3)(4)
TCK
X
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
Copyright © 2011–2012, Texas Instruments Incorporated
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