MSP430F673x
MSP430F672x
SLAS731A –DECEMBER 2011–REVISED APRIL 2012
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Port J, J.0, JTAG pin TDO, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVCC
0
1
PJOUT.x
00
01
10
11
From JTAG
SMCLK
PJ.0/SMCLK/TDO
PJDS.0
0: Low drive
1: High drive
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
Port J, J.1 to J.3, JTAG pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Pad Logic
PJREN.x
DVSS
DVCC
0
1
1
PJDIR.x
DVSS
0
1
PJOUT.x
00
From JTAG
01
10
11
PJ.1/MCLK/TDI/TCLK
PJ.2/ADC10CLK/TMS
PJ.3/ACLK/TCK
PJDS.x
0: Low drive
1: High drive
MCLK/ADC10CLK/ACLK
PJSEL.x
From JTAG
PJIN.x
Bus
Holder
EN
D
To JTAG
110
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