MSP430F663x
SLAS566C –JUNE 2010–REVISED AUGUST 2012
www.ti.com
INPUT/OUTPUT SCHEMATICS
Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
82
Copyright © 2010–2012, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
